Current electronic device manufacturing involves depositing layers of patterned materials on a substrate to fabricate transistors, contacts, and other devices. For proper operation of the device, these patterned layers for example contacts, lines and transistor features need to be aligned. Generally, an overlay control is defined as a control of the alignment of a patterned layer to one or more underlying patterned layers for a multi-layer device structure. Typically, an overlay error represents a misalignment between the patterned layers.
The misalignment between the patterned layers can cause short circuits and connection failures that impact manufacturing yield and cost. Generally, as the device features decrease and pattern density increases, overlay error budgets shrink. Conventional multi-exposure and multi-patterning schemes require very tight overlay error budgets. In conventional lithographic systems, various alignment mechanisms are provided to align features in a given layer to the features in a underlying layer. For advanced nodes, however, optical or extreme ultraviolet (EUV) scanner improvements alone does not reduce the overlay error enough to meet the required specifications. A process related overlay error has become a significant part (about 50%) of the overall overlay budget. Typically, the overlay error reduces the device performance, yield and throughput significantly. Additionally, a stress related process induced overlay error significantly impacts high volume production (HVP) of logic and memory devices.